The present invention relates to a non-uniform weighting circuitry for an encoder or decorder which is employed for analog-to-digital (A-D) conversion or for digital-to-analog (D-A) conversion of electric signals.
As new and more sophisticated communication services for audio, video and data communications as well as facsimiles (Fax) have been introduced in practical use, demand for communication systems having a high flexibility for instantly complying with many and various services has promoted developments of digital signal processing techniques such as digital transmission systems and digital converters. The heart of such digital signal processing techniques resides in encoders and decoders for A-D and D-A conversions of electric signals. In particular, in the field of communication, a non-uniform weighting circuitry imparted with non-uniform (non-linear) quantization characteristics is commonly used for the encoder and decoder with a view to reducing quantization noises at the time when signals of small magnitudes are processed. Performance as well as economy of the encoder and decoder depend on the non-uniform weighting circuit. For the non-uniform weighting circuitry there has been heretofore known a non-uniform weighting circuitry using an attenuator which is advantageous in that the circuit can be implemented in a simplified arrangement with a small number of component elements at a relatively strict requirement for accuracy imposed on operations of the circuit elements. For example, reference is to be made "Transmission Systems for Communications" published by Bell Telephone Laboratories Inc. (Fourth Edition, February 1970). The hitherto known non-uniform weighting circuitry such as referred to above allows the input and output characteristics of the encoder and decoder to be represented with segmental approximation with a plurality of line segments and is used for encoding amplitude information of a signal with a plurality of bits in total or decoding it. Among the bits, one bit is allotted for representing the signal polarity, some of bits are used for identifying the segment, and the remaining bits are used for representing steps in a single segment. To this end, the circuitry is composed of a polarity changing circuit, a constant current circuit, a variable attenuator and a uniform weighting circuit connected in a cascade configuration, as will be described hereinafter in detail. It is however noted in connection with the above described weighting circuit that inverter amplifiers are used in the polarity changing circuit and are required to be operated with a high accuracy, which in turn provides obstacle to the attempt for relaxing accuracy requirement imposed on the component elements of the whole circuits. Besides, addition of such inverter circuits will restrict the operating speed of the circuit.
As an attempt to obviate the difficulty described above, the inventors have already proposed an improved non-uniform weighting circuitry using an attenuator, as will be described hereinafter in detail in conjunction with FIG. 2 of the accompanying drawings (refer to, if necessary, Japanese Patent Application No. 126354/1975 filed Oct. 22, 1975). This improved circuit is of such arrangement that the polarity changing circuit is constituted by a constant current switching circuit and that the polarities of both bias currents applied to the uniform weighting circuit and the variable attenuator are changed in common by a drive signal from a polarity of bits. The improved circuit exhibits certainly many advantages as compared with the hitherto known circuit. However, due to the fact that the impedance of the variable attenuator can not be set arbitrarily at small values, spike-like noises generated by a switch which constitutes a part of the variable attenuator are undesirably superposed directly on the quantized output signal. An effort to reduce the influence of such spike-like noises will involve difficulty in attaining high speed operations of the encoder and the decoder.